VimGolfInstance creation in Verilog
Creating an instance of a module is a very frequent task in Verilog. Let's see how efficiently can it be done
Start file
module sram #( parameter AW = 12, parameter DW = 32 )( input clk, input rstn, input wr, input rd, input [AW-1:0] addr, input [DW-1:0] wdata, output [DW-1:0] rdata ); // here goes the SRAM model // ... endmodule
End file
wire w_clk;
wire w_rstn;
wire w_wr;
wire w_rd;
wire [ 7:0] w_addr;
wire [15:0] w_wdata;
wire [15:0] w_rdata;
sram #(
.AW (8),
.DW (16)
) i0_sram (
.clk (w_clk),
.rstn (w_rstn),
.wr (w_wr),
.rd (w_rd),
.addr (w_addr),
.wdata(w_wdata),
.rdata(w_rdata)
);
View Diff
1,15c1,20 < module sram #( < parameter AW = 12, < parameter DW = 32 < )( < input clk, < input rstn, < input wr, < input rd, < input [AW-1:0] addr, < input [DW-1:0] wdata, < output [DW-1:0] rdata < ); < // here goes the SRAM model < // ... < endmodule --- > wire w_clk; > wire w_rstn; > wire w_wr; > wire w_rd; > wire [ 7:0] w_addr; > wire [15:0] w_wdata; > wire [15:0] w_rdata; > > sram #( > .AW (8), > .DW (16) > ) i0_sram ( > .clk (w_clk), > .rstn (w_rstn), > .wr (w_wr), > .rd (w_rd), > .addr (w_addr), > .wdata(w_wdata), > .rdata(w_rdata) > );
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